The present invention relates generally to integrated circuit devices and, more particularly, to acquisition of silicon-on-insulator (SOI) switching history effect statistics.
History effects in partially depleted silicon-on-insulator (PD-SOI) technology are an important source of temporal variability. The delay of a circuit in PD-SOI depends on the circuit's previous switching activity. When a circuit initially switches after being at rest for a few milliseconds (ms) or more (1SW), it will have a different delay than when it switches again within a few nanoseconds (ns) of the initial event (2SW). The fractional difference of the 1SW and 2SW delays, referred to as the 1SW/2SW history, can be as much as 10% or more, and can be either positive with 2SW faster, or negative with 1SW faster. Steady state (SS) delay, as measured with a ring oscillator, typically lies somewhere between 1SW and 2SW. This behavior all derives from the floating body of PD-SOI, the potential of which directly modulates MOSFET threshold voltage (Vt) and is influenced by temperature, VDD, leakage currents, and capacitance.
History effect must be taken into account when gauging technology performance as measured, for example, with ring oscillators. It also impacts specific designs where the relative timing of different paths within a circuit is critical. In addition, the same mechanism that modulates delay also impacts SRAM operating margins. Both the average value of the history and its variation from one gate to the next are very important, as well as knowledge of the independent behavior of NFET (pulldown) and PFET (pullup) devices. While a number of techniques have been introduced to measure various aspects of history effect, at present there are no test structures for effective acquisition of data on the statistical variation of 1SW/2SW history within a large set of nominally identical circuits.
Experimental evaluation of history effects has typically involved high speed bench tests in an off-line setting. In one approach, the delays of a long chain of inverting devices in response to different input waveforms are analyzed. In this approach, the delays are determined and history components averaged over pullup and pulldown over a large number (e.g., 100 to 1000) gates. Recently, structures have been demonstrated for measuring some components of switching delay history using only low-speed inputs and outputs (I/O's). Such structures include long delay chain configurations that can be readily measured inline and provide history values to 2-3% precision, again averaged over pullup and pulldown and over a large number of gates. The simplified I/O requirements allow for the structures to be measured fairly rapidly in the manufacturing line.
In another approach, the difference in the delay of a (capacitively) loaded versus unloaded circuit is measured with sub-picosecond (ps) precision under different input conditions. The changes in this delay difference in response to changes in the input pulses can be used to deduce the various history components. This approach yields values for the pullup and pulldown components of history separately and for single devices, but under the assumption that the loaded and unloaded gates are identical. In this case, high-speed inputs and outputs are required. The necessary time resolved sampling measurements are relatively slow and cumbersome and not well suited for gathering statistics.